1. Field of the Invention
The invention relates to a display device, and more particularly such a display device having a light emitting element and a memory control circuit. The memory control circuit controls a writing and reading to memories such as SRAM.
2. Description of the Related Art
Hereinafter explained is a display device which disposes a light emitting element at each pixel and displays an image by controlling the emission of the light emitting elements.
The explanation throughout this specification uses elements (OLED elements) having a structure in which an organic compound layer for emitting light when an electric field is generated is sandwiched between an anode and a cathode, for the light emitting elements, but the present invention is not limited to this structure.
Further, the explanation within this specification uses elements that utilize light emitted when making a transition from singlet excitons to a base state (fluorescence), and those that utilize light emitted when making a transition from triplet excitons to a base state (phosphorescence).
An organic compound layer includes a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injection layer, and the like. The basic structure of a light emitting element is a laminate of an anode, a light emitting layer, and a cathode layered in this order. The basic structure can be modified into a laminate of an anode, a hole injection layer, a light emitting layer, an electron injection layer, and a cathode layered in this order, or a laminate of an anode, a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injection layer, and a cathode layered in this order.
A display device is constituted by a display and peripheral circuits for inputting signals to the display.
The structure of the display is shown in a block diagram of FIG. 8.
In FIG. 8, the display 2000 is constituted by a source signal line driver circuit 2107, a gate signal line driver circuit 2108, and a pixel portion 2109. The pixel portion has pixels disposed in a matrix shape.
Thin film transistors (hereafter referred to as TFTs) are arranged in each pixel. A method of placing two TFTs in each pixel and controlling light emitted from the light emitting element of each pixel is explained.
FIG. 9 shows a structure of a pixel portion of a display device.
Source signal lines S1 to Sx, gate signal lines G1 to Gy, and electric power source supply lines V1 to Vx are arranged in a pixel portion 2700, and x columns and y rows (where x and y are natural numbers) of pixels are also placed in the pixel portion. Each pixel 2705 has a switching TFT 2701, a driver TFT 2702, a storage capacitor 2703, and a light emitting element 2704.
The pixel is constituted by one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one electric power source supply line V of the electric power source supply lines V1 to Vx, the switching TFT 2701, the driver TFT 2702, the storage capacitor 2703, and the light emitting element 2704.
A gate electrode of the switching TFT 2701 is connected to the gate signal line G, and either a source region or a drain region of the switching TFT 2701 is connected to the source signal line S, while the other is connected to a gate electrode of the driver TFT 2702 and to one electrode of the storage capacitor 2703. Either a source region or a drain region of the driver TFT 2702 is connected to the electric power source supply line V, while the other is connected to an anode or a cathode of the light emitting element 2704. The electric power source supply line V is connected to one of the two electrodes of the storage capacitor 2703, namely the electrode on a side to which the driver TFT 2702 and the switching TFT 2701 are not connected.
The anode of the light emitting element 2704 is referred to as a pixel electrode, and the cathode of the light emitting element 2704 is referred to as an opposing electrode, within this specification for cases in which the source region or the drain region of the driver TFT 2702 is connected to the anode of the light emitting element 2704. On the other hand, if the source region or the drain region of the driver TFT 2702 is connected to the cathode of the light emitting element 2704, then the cathode of the light emitting element 2704 is referred to as the pixel electrode, and the anode of the light emitting element 2704 is referred to as the opposing electrode.
Further, an electric potential imparted to the electric power source supply line V is referred to as an electric power source electric potential, and an electric potential imparted to the opposing electrode is referred to as an opposing electric potential.
The switching TFT 2701 and the driver TFT 2702 may be either p-channel TFTs or n-channel TFTS. However, it is preferable that the driver TFT 2702 is a p-channel TFT, and that the switching TFT 2701 is an n-channel TFT for cases in which the pixel electrode of the light emitting element 2704 is the anode. Conversely, it is preferable that the driver TFT 2702 is an n-channel TFT, and that the switching TFT 2701 is a p-channel TFT if the pixel electrode is the cathode.
Operations during display of an image with the aforementioned pixel structure are explained below.
A signal is inputted to the gate signal line G, and the electric potential of the gate electrode of the switching TFT 2701 changes, then a gate voltage is changed. The signal is inputted to the gate electrode of the driver TFT 2702 by the source signal line S, via source and drain of the switching TFT 2701 which thus has been placed in a conductive state. Further, the signal is stored in the storage capacitor 2703. The gate voltage of the driver TFT 2702 changes in accordance with the signal inputted to the gate electrode of the driver TFT 2702, then the source and drain are placed in a conductive state. The electric potential of the electric power source supply line V is imparted to the pixel electrode of the light emitting element 2704 through the driver TF 2702. The light emitting element 2704 thus emits light.
A method of expressing gradations with pixels having such a structure is explained. Gradation expression methods can be roughly divided into an analog method and a digital method. The digital method has advantages of being good at variation of TFTs compared with the analog method. A digital gradation expression method is focused upon here. A time gradation method can be given as the digital gradation expression method. A time gradation driving method is explained in detail now.
The time gradation driving method is a method of expressing gradations by controlling the period that each pixel of a display device emits light. If a period for displaying one image is taken as one frame period, then one frame period is divided into a plurality of subframe periods.
Turn on and turn off, namely whether or not the light emitting element of each pixel is made to emit light or to not emit light, is performed for each subframe period. The period during which the light emitting element emits light in one frame period is controlled, and a gradation for each pixel is expressed.
The time gradation driving method is explained in detail using timing charts of FIGS. 10A and 10B. Note that an example of expressing gradation using a 4-bit digital image signal is shown in FIGS. 10A and 10B. Note also that FIG. 9 may be referred to regarding the structure of the pixel portion and the structure of the pixels, respectively. In accordance with an external electric power source (not shown in the figure), the opposing electric potential can be switched over between an electric potential on the same order as the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential), and an electric potential difference of the electric power source supply lines V1 to Vx on an order sufficient to make the light emitting element 2704 emit light.
One frame period F is divided into a plurality of subframe periods SF1 to SF4. The gate signal line G1 is selected first in the first subframe period SF1, and a digital image signal is inputted from the source signal lines S1 to Sx to each of the pixels having the switching TFTs 2701 with gate electrodes connected to the gate signal line G1. The driver TFT 2702 of each pixel is placed in an ON state or an OFF state by the inputted digital image signal.
The term “ON state” for a TFT in this specification indicates that the TFT is in a state in which there is a state of conduction between the source and the drain in accordance with a gate voltage. Further, the term “OFF state” for a TFT indicates that there is a non-conductive state between the source and the drain in accordance with a gate voltage.
The opposing electric potential of the light emitting elements 2704 is set nearly equal to the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential) at this point, and therefore the light emitting elements 2704 do not emit light even in pixels having their driver TFT 2702 in an ON state. The aforementioned operations are repeated for all of the gate signal lines G1 to Gy, and a write-in period Ta1 is completed. Note that a period for write-in during the first subframe period SF1 is called Ta1. In general, a write-in period of a j-th sub-frame period (where j is a natural number) is called Taj.
The opposing electric potential changes when the write-in period Ta1 is complete, so as to have an electric potential difference from the electric power source electric potential on an order so that the light emitting element 2704 will emit light. A display period Ts1 thus begins. Note that the display period of the first subframe period SF1 is called Ts1. In general, a display period of the j-th sub-frame period (where j is a natural number) is denoted by using a reference symbol Tsj. The light emitting elements 2704 of each pixel are placed in a light emitting state or a non-light emitting state, corresponding to the inputted signal, in the display period Ts1.
The above operations are repeated for all of the subframe periods SF1 to SF4, one frame period F1 is completed. The length of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set appropriately here, and gradations are expressed by an accumulation of the display periods of the subframe period during which the light emitting elements 2704 emit light. In other words, the total amount of the turn on time within one frame period is used to express the gradations.
A method of generally expressing 2n gradations by inputting an n-bit digital video signal, is explained. One frame period is divided into n sub-frame periods SF1 to SFn at this point, for example, and the ratios of the lengths of the display periods Ts1 to Tsn of the sub-frame periods SF1 to SFn are set so as to be Ts1:Ts2: . . . :Tsn=20:2−1:2−n+2:2−n+1. Note that the lengths of the write-in periods Ta1 to Tan are all the same.
Within one frame period, the gradation of the pixels in the frame period is determined by finding the total of the display period Ts during which a light emitting state is selected in the light emitting element 2704. For example, if the brightness for a case in which a pixel emits light during all of the display periods is taken to be 100% when n=8, then a brightness of 1% can be expressed if the pixel emits light in the display period Ts8 and in the display period Ts7. A 60% brightness can be expressed for cases in which the pixel emits light in the display periods Ts6, Ts4, and Ts1.
A circuit to convert signals is needed in order to display in such time gradation method as shown above. Schematic of the conventional control circuit is shown in FIG. 2. A control circuit 200 is constituted by memories A201 and B202 for storing data, a logic circuit for reading data and writing into the memory (W-LOGIC 203), and a logic circuit for reading the memory and outputting data (R-LOGIC 204).
A timing chart of the conventional control circuit is shown in FIG. 3. Data is written and read alternately using memories A201 and B202, in order to make the digital data inputted to W-LOGIC 203 synchronize with a time gradation method.
When R-LOGIC204 reads a signal in the memory A201, a digital video signal for the next frame period is inputted to the memory B202 through W-LOGIC 203 and starts being stored.
In this way, the control circuit 200 includes the memories A201 and B202 which can store digital video signal of 1 frame period each, to sample a digital video signal by using them alternately.
Conventionally, however, there was a state of Wait until the next read signal occurred after writing into the memories A201 and B202. A switching function between writing and reading of the memories A201 and B202 was operated in timing with reading which takes more time. (FIG. 3)